1. Field of the Invention
This invention relates to a system and method for high-efficiency checkerboard memory self-test. More particularly, the invention is an on-chip system and method for performing checkerboard self-test of memory circuits.
2. Description of the Related Art
Numerous methods have been proposed for the testing of integrated circuitry. Typically, a black box technique is used. In this technique, a circuit is provided with a deterministic stimulus, thereby generating a response from the circuit, which is compared to a known expected output. Based on the comparisons, the circuit is determined to be simply good or bad. Past problems with the testing of integrated circuitry are the large test data volumes and long test times.
Self-test refers to the presence of testing circuits which are on a component containing the circuits to be tested. The component may be a card, wafer, or an integrated circuit chip. Thus, self-test may be accomplished with testing circuits integrated into the circuits to be tested (i.e., on-chip), or located externally on the component (i.e., off-chip). The choice between on-chip and off-chip testing requires balancing two competing factors. Off-chip testing is advantageous because the resting circuits need not be reproduced with the production of each integrated circuit chip. On-chip testing is considered advantageous because of its closeness to the circuits being tested, thereby making testing available at significantly higher speeds than for off-chip testing and requiring little more than an external power supply therefor. In recent years, the balance has swung in favor of on-chip testing because the increase in integrated circuit density available has reduced the emphasis on chip real estate and increased the emphasis on testing speed.
On-chip circuit testing can be divided into areas of logic circuit testing and memory circuit testing. For both types of on-chip testing it is desirable to be able to test all storage points in both the logical zero and one states. Due to recent increases in on-chip circuit density, it is becoming more likely that integrated circuit chips will contain both logic and memory circuits. Thus, there is an increasing need to be able to test both logic circuits and memory circuits on the same chip. However, most known circuit testing techniques are directed merely to the testing of logic circuits.
The problem presented by the testing of logic circuits is the accessibility and observability of the logic circuit storage elements (latches). These storage elements are typically intertwined in such a manner that data cannot be inputted into a particular logic circuit storage element independently of other storage elements. Control of the independent logic circuit storage elements is required for logic circuit testing so that a known stimulus can be provided to the logic circuits, and the results can be observed. This problem has been solved by level sensitive scan design (LSSD) techniques. ISSD techniques are widely known, as described, for example, in U.S. Pat. Nos. 3,761,695 or 3,783,254.
LSSD testing is implemented by imparting a shift register capability to each of the logic system latches and by making these shift register latches (SRL's) accessible during an input/output mode. LSSD testing requires operation of the logic circuits in two separate modes. In the first mode, known test data is serially inputted and shifted to the appropriate SRL locations. With the SRL initialized to a known state, operation of the logic circuits in the second mode begins. Known test data is thus propagated through the logic circuits to act as a stimuli to the system, the results being captured in the SRL's. Upon reversion to the original mode of operation, the status of the SRL's can be outputted and compared with known data which would be present if the circuitry operated correctly.
LSSD logic circuit testing is convenient because it permits sequential logic to be tested as combinatorial logic. In recent years, however, such "deterministic" circuit testing has become increasingly expensive. Circuit density has increased so rapidly that it is no longer feasible to provide for input/output (i.e., accessibility and observability) at each logical storage element. The same problem makes this technique impractical for memory test as well. Thus, more efficient techniques are required for the testing of circuits.
Another known technique for circuit testing is signature analysis. Known test data patterns are again used to stimulate logic or memory circuits. Data outputted from the stimulated circuits are then fed into a logic circuit which compresses the data into a data signature. The data signature is then compared to the data signature which would result had the logic or memory circuits functioned properly. Examples of such signature analysis can be seen in U.S. Pat. Nos. 4,597,080 and 4,601,034.
The advantage of signature analysis over simple deterministic testing is the compression of the outputted test data. The storing of test data for each output response is no longer required, thereby reducing tester complexity and test data volume. Although this feature also prevents the ability to easily determine the precise location of a circuit failure, such is irrelevant because the high circuit density and low cost of integrated circuit chips has made it impractical to repair a detected failure. Instead, a failed chip is discarded and another substituted in its place.
Despite the aforementioned advantages, signature analysis is not a sufficiently efficient technique for testing the circuit densities achievable today. Large amounts of circuits are still required to initialize highly dense logic and memory circuits. Recent techniques for testing logic circuits are disclosed in U.S. Pat. Nos. 4,513,418 and 4,519,078. These techniques employ a random pattern generator, including a linear feedback shift register, provided with known seed data (not all zeros) to apply a set of data patterns to test LSSD logic circuits. A random pattern generator cycle is herein defined as the period of time beginning with seeding and ending when the seed data reappears in the shift register. The efficient generation of memory addresses requiring initialization is a particular problem heretofore not resolved by these techniques. A random pattern generator simply having the same number of stages as there are address lines required for memory addressing will not cycle through all memory addresses. For example, the exclusive OR gate(s) in the feedback loop inevitably receive and therefore return a logical one to the initial stage of the shift register, thereby preventing the generation of the memory address consisting of all zeros. This is good in the sense that the presence of all zeros in the shift register would cause the random pattern generator to repeat the all zero state because the exclusive OR gate feedback loop would never generate anything but additional zeros. However, the all zero address must still be generated for complete testing. Thus, a simple system and method for generating the memory address consisting of all zeros is required.
The inability of linear feedback shift registers to generate patterns including the all zero state has been recognized. One publication merely recommends modification of the shift register without further specification. McCluskey, E. J., "Built-In Self-Test Techniques," IEEE Design and Test, April, 1985, pp. 21-28. Another publication suggests modification of the existing stages or feedback loop of the shift register to generate the all zero state. Wang, L. and McCluskey, E. J., "Feedback Shift Registers For Self-Testing Circuits," VLSI Systems Design, Dec., 1986, pp. 50-58 and McCluskey, E. J. and Bozorgui-Nesbat, S., "Design for Autonomous Test," IEEE Transactions on Computers, Vol. c-30, No. 11, November, 1981, pp. 866-875. However, the proposed modifications render the shift register non-linear or the feedback loop more complex than a simple exclusive OR gate. Thus, these publications do not solve the aforementioned problems.
Regarding logic testing only, the addition of a stage to a linear feedback shift register has been proposed to allow for an all zero output window. Bardell, P. H. and McAnney, W. H., "Pseudorandom Arrays for Built-In Tests," IEEE Transactions on Computers, Vol. c-35, No. 7, July, 1986, pp. 653-58. The output window is an array of data, the rows of which are formed from the data present in some of the stages of the shift register at various times during the data pattern. However, the array is generated inefficiently, using only a small portion of the existing stages of the shift register. This is because the proposal is directed to the generation of the all zero state in the entire array, not the generation of an all zero state in the shift register. The number of stage in the shift register do not correspond to the number of lines needed for addressing, and are reduced only by a complex logic circuit for inputting data from the shift register into the array. Furthermore, the complexity of the logic circuit makes it difficult to adapt to a particular memory size.
The simple generation of all memory addresses for on-chip self-test of memory is addressed in co-pending U.S. Pat. application Ser. No. 187,708, Memory Self-Test, Hack, hereby incorporated by reference. A random pattern generator configuration includes a linear feedback shift register containing at least one more stage than address lines needed for addressing the memory. The data from the additional random pattern generator stages are not used in so far as memory addressing is concerned. The random pattern generator design is based upon a primitive polynomial. Such a random pattern generator ensures that cycling through all possible combinations of the test data patterns accounts for each memory address in the memory circuits, including the address of all zeros. The all-zero address is accounted for when the random pattern generator generates all zeros, except for a logical one in at least one of the additional stages of the shift register. Exhaustive coverage of the memory addresses may also be accomplished by using non-linear configurations or reversible deBruijn counters.
The generation of each possible memory address makes it possible to determine if each memory location is capable of achieving both memory states. This is known as "functional" testing. Despite functional testing, a need still exists to verify that there is no interaction between physically adjacent memory cells. For example, the ability of a particular memory cell to achieve a particular memory state could be dependent on the memory state of one or more of its neighboring memory cells.
It is known to use checkerboard memory tests to verify that there is no interaction between adjacent memory cells. Examples of such checkerboard memory tests are disclosed in U.S. Pat. Nos. 4,502,131; 4,654,849; IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 26, No. 3A, August 1983, pps. 1078-1079; and IBM TECHNICAL, DISCLOSURE BULLETIN, Vol. 21, No. 12, May 1979, pps. 4911-4913. Typically, an alternating zero and one pattern is written into the memory array and read back out followed by the writing of the complimentary pattern and its reading. Because a checkerboard memory test would normally be performed in conjunction with a functional memory cell test verifying that the controls and address circuitry are operating correctly, it is desirable that both tests be able to utilize some or all of the same circuitry. The use of common circuitry would improve the efficiency of testing and minimize the physical space required for the circuits for both tests.